The present invention relates to an error processor and, more particularly, to a processor disposed on one integrated circuit chip that includes processing hardware and an interface therefor.
In any digital system where data is transmitted and received, one or more of the data bytes may be received in error. This has been a problem from the time data processing systems were first invented.
As more sophisticated data processing operations are performed, involving more complex equipment, there is a greater need for systems to detect and correct errors in data transfers. For example, operations such as merging files, sorting of data within files, numerical/statistical analyses, complex data handling procedures and word processing operations require increased reliability in data transfer. In the field of telecommunications and telemetry, error rates tend to increase when data is transmitted over analog lines at high baud rates. If data errors occur and are undetected, valuable information and system operation itself may be affected. Thus, error detecting and correcting features are not only advantageous, they are required to improve system integrity.
In response to the problem of error generation during data transfers, systems have been developed to detect such errors. One of the earliest methods for detecting errors was the parity check code. A binary code word has odd parity if an odd number of its digits are 1's. For example, the number 1011 has three 1 digits and therefore has odd parity. Similarly, the binary code word 1100 has an even number of 1 digits and therefore has even parity.
A single parity check code is characterized by an additional check bit added to each data word to generate either odd or even parity. An error in a single digit or bit in a data word would be discernible since the parity check bit associated with that data word would then be reversed from what is expected. Typically, a parity generator adds the parity check bit to each word before transmission. This technique is called padding the data word. At the receiver, the digits in the word are tested and if the parity is incorrect, one of the bits in the data word is considered to be in error. When an error is detected at a receiver, a request for a repeat transmission can be given so that the error can be corrected. Only errors in an odd number of digits can be detected with a single parity check, since an even number of errors results in the parity expected for a correct transmission. Moreover, the specific bit in error cannot be identified by the parity check procedure as hereinabove described.
A more sophisticated error detection system was later devised. Data words of a fixed length of bits were grouped into blocks of a fixed number of data words each. Parity checks were then performed between different data words as well as for each individual data word. The block parity code detected many patterns of errors and could be used not only for error detection, but also for error correction when an isolated error occurred in a given row and column of the matrix. While these geometric codes were an improvement over parity check bits per se, they still could not be used to detect errors that were even in number and symmetrical in two dimensions.
After parity check codes and geometric codes were devised, a code was invented by Hamming, after whom it is named. The Hamming code is a system of multiple parity checks that encodes data words in a logical manner so that single errors can be not only detected but also identified for correction. A transmitted data word used in the Hamming code consists of the original data word and parity check digits appended thereto. Each of the required parity checks is performed upon specific bit positions of the transmitted word. The system enables the isolation of an erroneous digit, whether it is in one of the original data word bits or in one of the added parity check bits.
If all the parity check operations are performed successfully, the data word is assumed to be error free. If one or more of the check operations is unsuccessful, however, the single bit in error is uniquely determined by decoding so-called syndrome bits, which are derived from the parity check bits. It should be noted once again that only single bit errors are detected and corrected by use of the conventional Hamming code. Double bit errors, although detectable by the Hamming code, are not correctable.
The Hamming code is only one of a number of codes, generically called error correcting codes (ECC's). Codes are usually described in mathematics as closed sets of values that comprise all the allowed number sequences in the code. In data communications, transmitted numbers are essentially random data patterns which are not related to any predetermined code set. The sequence of data, then, is forced into compliance with the code Set by adding to it at the transmitter, as hereinabove mentioned. A scheme has heretofore been developed to determine what precise extra string to append to the original data stream to make the concatenation of transmitted data a valid code. There is a consistent way of extracting the original data from the code value at the receiver and to deliver the actual data to the location where it is ultimately used. For the code scheme to be effective, it must contain allowed values sufficiently different from one another so that expected errors do not alter an allowed value such that it becomes a different allowed value of the code.
A cyclic redundancy code (CRC) consists of string of binary data evenly divisible by a generator polynomial, which is a selected number that results in a code set of values different enough from one another to achieve a low probability of an undetected error. To determine what to append to the string of original data, the original string is divided as it is being transmitted. When the last data bit is passed, the remainder from the division is the required string that is added since the string including the remainder is evenly divisible by the generator polynomial. Because the generator polynomial is of a known length, the remainder added to the original string is also of fixed length.
At the receiver, the incoming string is divided by the generator polynomial. If the incoming string does not divide without remainder, an error is assumed to have occurred. If the incoming string is divided by the generator polynomial without remainder, the data delivered to the ultimate destination is the incoming data with the fixed length remainder field removed.
The efficiency of error detecting and correcting hardware can be improved by a technique called data interleaving. A block of data being transmitted is partitioned into separate subdivisions and each subdivision is treated as an independent data block for error detection and correction purposes. This makes a large error occurring in the data block appear as a smaller error in a subdivision since it is split between two subdivisions.
Error correcting codes called Reed-Solomon codes are especially effective in byte oriented transmission protocol and are being increasingly used in disk and communications systems.
In previous computer systems, error control related tasks occurred in discrete steps. An operating engine or processor would generate syndromes but the syndromes would have to be evaluated elsewhere. Similarly, when checkbytes were to be generated, they would be generated using a software program. Thus, previous systems have required separate components for performing the various steps in error detection and correction. Because of the multiple components required, additional expense and concomitant time delays were often needed.
In the earliest systems, all error detection and correction activities were performed in software. Later, hardware was available to perform checkbyte and syndrome generation operations, but software was still required to evaluate the syndromes and then to correct the erroneous data. The use of software in these systems is time consuming and inefficient.
It would be advantageous to provide checkbyte and syndrome generator operation in hardware.
It would also be advantageous to provide a hardware engine or processor with an interface on one integrated circuit chip.
It would also be advantageous to provide syndrome analysis in hardware.
It would also be advantageous to provide a mechanism for generating correction vectors when errors are detected and to include this mechanism in an error processor on a single chip.
It would also be advantageous to signal other components that a vector is available so that no polling or interrupt activities need be pursued.